[LAB Exploration] New Memory Structure Discovered to Drive AI Semiconductor Performance

Joint Research Team from Korea University and DGIST
Achieves 7.6-Fold Increase in Speed, Paving the Way for Next-Generation 3D Chip Applications

A technology capable of dramatically improving the accuracy and processing speed of memory semiconductors, which are critical to the performance of artificial intelligence (AI) semiconductors, has been developed by a Korean research team. Compared to conventional methods, this structure can achieve more than 100 times higher data accuracy and a 7.6-fold increase in read speed.

Next-generation semiconductor device research conducted by (from left) Jongyun Park, Ph.D. candidate in the Department of Electrical and Electronic Engineering at Korea University, and Hyunyong Yoo, professor in the Department of Electrical and Electronic Engineering at Korea University. Korea University

Korea University announced on May 15 that a joint research team led by Professor Yoo Hyunyong of the Department of Electrical and Electronic Engineering at Korea University and Professor Kwon Hyukjun of the Daegu Gyeongbuk Institute of Science and Technology (DGIST) has implemented a "complementary gain cell (CGC)" structure by combining p-channel silicon with n-type oxide semiconductors.

In the semiconductor industry, 3D stacking technology, which vertically stacks multiple semiconductors, is garnering attention as a next-generation memory technology. However, there have been issues with reduced data read accuracy due to interference among devices that occurs during the low-temperature process. The research team addressed this challenge by implementing the CGC structure, which combines n-type oxide semiconductors and p-channel silicon. The n-type oxide semiconductor offers advantages such as reduced power consumption and enhanced data retention, while the p-channel silicon excels in fast and stable information reading.

The team also utilized the previously problematic capacitive coupling phenomenon as a voltage amplification mechanism. As a result, the sensing margin—a performance indicator for accurate data reading—improved by more than 100 times compared to existing approaches. The researchers explained, "Stable operation is possible even in environments where 1,024 cells are interconnected."

In addition, through the low-temperature process, they achieved the world's largest grain size for laser-crystallized silicon devices. Generally, the larger the grain size, the faster the semiconductor operates. The CGC structure demonstrated an operating speed approximately 7.6 times faster than conventional oxide semiconductor-based cells. Data retention performance also reached the highest level, improving by more than 100 times compared to previous technologies.

Professor Yoo stated, "This technology will become a fundamental platform that accelerates the commercialization of 3D stacked semiconductors," adding, "We expect it to be utilized in the development of high-performance AI chips and high-capacity memory semiconductors in the future."

This research outcome will be presented next month at the world's most prestigious conference in the field of semiconductor devices, the Symposium on VLSI Technology & Circuits (2026 IEEE/JSAP Symposium on VLSI Technology & Circuits).

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