Development of Key Material to Reduce Semiconductor Production Power Consumption by 95%

ETRI Research Team "Localization of Advanced Semiconductor Chiplet Packaging Technology"

A domestic research team has developed advanced artificial intelligence (AI) semiconductor core material technology that can drastically shorten the process and reduce power consumption by up to 95%.

Advanced semiconductor chiplet integration process scene developed by ETRI. Photo by ETRI

The Electronics and Telecommunications Research Institute (ETRI) announced on the 28th that it has developed a new material essential for semiconductor processes for the first time in the world using its proprietary nano material technology. This is a core source new material technology development in the packaging field, which holds the key to cutting-edge semiconductor development, and it is expected to be used as a core material technology for manufacturing high-performance AI semiconductors required in autonomous driving, data centers, and other applications.

This is a revolutionary semiconductor chiplet packaging technology that can reduce power consumption by 95% compared to the existing technology held by Japan. The number of process steps has also been drastically reduced from nine to three. The process consists of three steps: attaching a non-conductive film (NCF), a new material developed by the researchers, to the semiconductor wafer, then irradiating the chiplet, which looks like a tile, with a surface laser to cure it.

Until now, the semiconductor industry has mainly used Japanese materials for advanced semiconductor packaging processes. However, the process involved a total of nine steps, used various complex equipment, and had major drawbacks such as high power consumption, cleanroom maintenance costs, and harmful substance emissions.

Global semiconductor companies such as Taiwan Semiconductor Manufacturing Company (TSMC), Intel, and Samsung Electronics are accelerating the development of new integration technologies for high-density chips made with cutting-edge semiconductors at the scale of a few nanometers (nm). Existing technologies had limitations such as the inability to clean the bonding interface, which serves as the connection path between chips at the scale of tens of micrometers (μm) required by chiplet integration technology, and the difficulty of bonding at room temperature.

The research team succeeded in improving this after more than 20 years of core source technology research by utilizing their proprietary nano material design technology and nano new materials. After applying the developed nano new material to an advanced semiconductor wafer substrate, tiles are made with chiplets produced from various wafers, and the bonding process is completed by irradiating with a surface laser for about one second, followed by a post-curing process. This new material is a polymer film, a nano material of epoxy-based material with a thickness of 10 to 20 nanometers (nm) with added reducing agents. When this material is irradiated with a laser, it solves all the steps from cleaning, drying, coating, to curing in the semiconductor post-process (packaging) stage.

Previously, chips separated from the wafer were attached to a board and cut one by one for use, but the new material developed by the research team allows chiplets to be directly stamped onto the wafer substrate like attaching tiles. The simplified process reduces the entire production line length from over 20 meters to 4 meters, which is 20% of the original. It also has the advantage of not requiring nitrogen gas, thus preventing the generation of harmful substances. This is a high-precision process applicable to advanced chiplet packages. It is the world's first integration process possible at room temperature (25℃). Existing processes all heated the stage temperature to 100℃, which caused not only power consumption but also increased errors due to thermal expansion and reliability degradation.

The research team explained, "Using nano material design technology activated above a characteristic temperature change, we have developed the world's first new material and new process that enable bonding at room temperature stage without smoke generation caused by temperature rise." They added, "Micro LED-related startups in the U.S. as well as world-leading foundry companies in the advanced semiconductor field are conducting processability and reliability evaluations, and commercialization is expected within three years if the evaluations are favorable." They continued, "This technology can provide an answer to the low-power and eco-friendly processes required by semiconductor display companies," and "We plan to expand the scalability and applicability of the technology by applying it to advanced chiplet integration and micro LED transfer and bonding processes."

This content was produced with the assistance of AI translation services.