"Accurate to 1 Trillionth of a Second"... Development of Ultra-Precise Clocks for Semiconductors

KAIST Research Team Reduces Power Consumption and Heat Generation to 1/100

A domestic research team has invented a clock (synchronization signal) used for ultra-high-density semiconductor manufacturing. This technology sends signals with accuracy up to one quadrillionth of a second, enabling circuits within the chip to operate synchronously, which is expected to help improve performance by reducing power consumption and heat generation.

KAIST announced on the 9th that a research team led by Professor Kim Jung-woon of the Department of Mechanical Engineering has developed a technology that can generate and distribute ultra-low noise clock signals within semiconductor chips using lasers.

As semiconductor chip performance has rapidly improved recently, the technology to supply clock signals that synchronize the operation of various circuit blocks within the chip with more precise timing has become increasingly important. Previously, the accuracy of clock signals was typically at the picosecond level (one trillionth of a second), but with the newly developed technology, clock signals with femtosecond-level accuracy (one quadrillionth of a second), which is far superior to existing methods, can be generated and distributed within the chip. Additionally, heat generation within the chip caused during clock distribution can be drastically reduced.

The research results were published on the 24th of last month in the international academic journal Nature Communications.

To distribute clock signals within high-performance semiconductor chips, many clock drivers must be used in the clock distribution network (CDN), which increases heat generation and power consumption, as well as degrades clock timing. The clock timing within the chip is determined by jitter, which is a rapidly and randomly changing variation, and skew, which is the difference in clock arrival times between different points within the chip. As the number of clock drivers increases, both jitter and skew typically grow to several picoseconds or more.

Schematic diagram, principle, and performance comparison of an optical-based clock distribution network. Image source: Provided by KAIST

To solve this problem, the research team introduced a new type of clock distribution network technology that uses an optical frequency comb laser with jitter below the femtosecond level as the master clock. This method converts optical pulses generated by the optical frequency comb laser into photocurrent pulses using a high-speed photodiode, then generates square wave clock signals by charging and discharging a metal-structured clock distribution network within the semiconductor chip.

In particular, by using this technology, clock distribution within the chip can be achieved solely through the metal structure without clock drivers in the clock distribution network, improving timing performance and drastically reducing heat generation within the chip. As a result, jitter and skew were reduced to below 20 femtoseconds, about 1/100th of previous levels, demonstrating excellent timing performance. Power consumption and heat generation during clock distribution within the chip were also reduced to about 1/100th compared to conventional methods.

Professor Kim said, "We are currently conducting research to improve performance by supplying sampling clock signals with very low jitter to high-speed circuits such as analog-to-digital converters," and added, "We also plan to conduct follow-up research on whether heat generation can be reduced in structures like 3D stacked chips."

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