Honored at DesignCon 2025 International Conference
with a Paper on "Power Integrity Design Based on Power Supply Noise Induced Jitter Using AI"

Dr. Shin Tae-in (28), a member of Professor Kim Jung-ho's laboratory (KAIST TERA Lab) in the Department of Electrical Engineering at the Korea Advanced Institute of Science and Technology (KAIST), was selected as the recipient of the 'Best Paper Award' at the international semiconductor design conference ‘DesignCon 2025’.

Dr. Shintaein

Dr. Shintaein

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A representative from TERA Lab explained on the 4th, “Dr. Shin Tae-in received high evaluations from the judges for contributing to technological innovation in the field among about 100 papers submitted and accepted by the end of 2024.” DesignCon is an internationally recognized conference in the semiconductor and package design fields.


Dr. Shin’s paper is titled “PSIJ Based Integrated Power Integrity Design for HBM Using Reinforcement Learning: Beyond the Target Impedance.”


In this paper, Dr. Shin proposed a methodology that optimizes the design by utilizing artificial intelligence (AI) to analyze design factors affecting jitter based on power supply noise induced jitter, which includes temporal information, for power integrity design of high-bandwidth memory (HBM) packages, drawing significant attention.


In particular, the TERA Lab representative emphasized that “Dr. Shin’s paper received high praise from the judges for verifying that the limitations of conventional impedance-based power distribution network design can be effectively overcome to improve power integrity by using AI reinforcement learning and power supply noise induced jitter, as well as for the originality of the AI-based research.”


Dr. Shin Tae-in stated, “For next-generation HBM-based package systems that are becoming increasingly faster to implement large-scale AI, I aim to establish the foundation for semiconductor signal and power integrity design based on the proposed methodology.” Dr. Shin also won the Best Paper Award at the same event three years ago.



Professor Kim Jung-ho’s laboratory currently has 27 students in total, including 17 master's and 10 doctoral candidates, conducting research to optimize various packages and interconnection designs involved in semiconductor front-end and back-end processes using AI machine learning (ML) techniques such as reinforcement and imitation learning. Additionally, research related to HBM-based computing architectures for large-scale AI implementation is also underway.


This content was produced with the assistance of AI translation services.

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