[Peace&Chips] Intel Unveils 2nm New Technology... Foundry Technology Competition Heats Up

3 Major Semiconductor Conferences 'VLSI Symposium' Held
Foundry Industry's Next-Generation Technology Competition Intensifies
Intel Unveils 'PowerVia', Samsung Reveals '3nm 2nd Generation'

Editor's NoteSemiconductors, known as the rice of modern industry. Although it's a term we hear every day, it's often hard to explain. Peace & Chips will make the complex concepts and overall trends of the semiconductor industry easy to digest for you. Just bring your spoon.

The 'VLSI Symposium 2023' was held on the 11th in Kyoto, Japan. VLSI is considered one of the world's top three semiconductor conferences alongside ISSCC and IEDM. It is an annual event held alternately in the United States and Japan, where outstanding papers are selected and presented each year. It is also a venue where key players from major global semiconductor companies, institutions, and universities gather to discuss next-generation technologies.

This year at VLSI, next-generation technology presentations from foundry (semiconductor contract manufacturing) companies are expected to continue. In particular, U.S.-based Intel attracted attention by announcing that it would introduce a new technology called 'PowerVia,' which is planned to be applied to its 2-nanometer (nm; 1 nm = one billionth of a meter) foundry process at this event.

PowerVia is an innovative technology that reverses the traditional method of supplying power to semiconductor chips. For a semiconductor to operate, it needs electricity, and the key point is relocating the power wiring, which was previously placed on the front side of the chip, to the backside. To achieve this, Intel reduced the wafer thickness and utilized nano Through-Silicon Via (TSV) technology.

Image of a test chip (processor) applying Intel's PowerVia technology / [Image provided by Intel]

Semiconductor chips are created through numerous processes on a silicon circular substrate called a wafer. First, circuits are drawn on the front side of the wafer. Then, wiring is done according to the drawn circuits. This involves creating paths that connect individual transistors (devices) within the circuit to enable signal transmission and power supply. At this stage, both signal wiring and power wiring are placed on top of the transistors.

Intel saw limitations in this method. As semiconductor technology advances and processes become finer, the circuit line widths narrow, inevitably reducing wiring area. In such cases, the overlapping of signal and power wiring areas causes noise and other issues.

Intel believed that by placing power wiring beneath the transistors, separating it from signal wiring, interference could be reduced while improving power efficiency and chip performance. After initially announcing the introduction of PowerVia in 2021 and conducting extensive research, Intel reported that a test processor (central processing unit, CPU) applying PowerVia achieved a 6% increase in clock (operating) speed and reduced voltage drop (loss) during packaging by 30%.

Intel plans to introduce PowerVia along with RibbonFET in its 20-angstrom (?; 1 ? = 0.1 nm) and 18 ? processes. If the roadmap proceeds as announced, new technologies will be realized in the 2 nm process in the first half of next year and the 1.8 nm process in the second half. RibbonFET is Intel's proprietary name for the next-generation transistor structure called Gate-All-Around (GAA) technology.

Global Foundry Market Share Trends (Q3 2021 - Q1 2023) / [Image Source=Counterpoint Research]

Samsung Electronics will showcase the specifications of its 3 nm second-generation process (SF3) at this event. Following the start of mass production of the 3 nm first-generation process (SF3E) in June last year, Samsung is preparing for SF3 mass production next year and is introducing detailed specifications for the first time. According to pre-released materials, SF3 improves the GAA technology first introduced in SF3E, achieving 34% better power efficiency and 22% higher performance compared to the 4 nm process.

TSMC is also expected to present various technologies available in its 3 nm process. Discussions on several technologies, including integrated system expansion solutions supporting high-performance computing and quantum computing, are also anticipated. As the foundry market grows, competition among companies in technology is intensifying.

According to first-quarter foundry market statistics released by market research firm Counterpoint Research, TSMC recorded a 59% market share, ranking first. Samsung Electronics holds 13%, ranking second. Intel's market share is minimal as it declared its re-entry into the foundry market in 2021. While Samsung is busy narrowing the gap with TSMC, Intel aims to become the second-largest foundry company by 2030.

This article is from [Peace & Chips], published weekly by Asia Economy. By clicking subscribe, you can receive articles for free.

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This content was produced with the assistance of AI translation services.