UNIST Develops Ultra-Compact Power Management Semiconductor to Lead the Era of 6G Communication and AI SoC Chips

Professor Heein Yoon's Team at UNIST Develops High-Performance Ultra-Compact Hybrid Power Management LDO
Low-Power Semiconductor with Outstanding Voltage Stabilization and Noise Filtering Published in IEEE JSSC

An ultra-compact semiconductor has been developed that stabilizes the voltage of electricity supplied to the main chips in smartphones and artificial intelligence devices, while also filtering out noise.

The power management performance has reached a world-class level, and the size has been further reduced. This advancement is expected to aid the development of highly integrated system-on-chip (SoC) solutions, such as AI semiconductors where computational cores operate continuously and cause significant voltage fluctuations, as well as 6G communication chips that are sensitive to noise.

The research team led by Professor Heein Yoon from the Department of Electrical and Electronic Engineering at UNIST has developed an ultra-compact hybrid power management semiconductor LDO.

Research team, (from left) Professor Heein Yoon, Researcher Changmin Ahn (first author), Researcher Hyokyung Ahn, Researcher Hyunjun Nam. Provided by Ulsan National Institute of Science and Technology (UNIST)

LDO is a semiconductor that manages the power supplied to the main semiconductor. For example, when a smartphone game app is suddenly turned on or off, the current usage changes rapidly, causing voltage fluctuations. The LDO detects these voltage swings and filters out the alternating current noise mixed into the direct current voltage.

The developed LDO features a hybrid structure that combines the advantages of analog and digital circuits, providing both the excellent voltage stabilization of digital circuits and the noise suppression capabilities of analog circuits.

In practice, this LDO was able to suppress output voltage fluctuations to 54 mV even when there was a current variation of 99 mA, and restored the voltage to its original state within 667 nanoseconds. Its noise suppression performance (PSRR) also reached -53.7 dB (at a 100 mA load and 10 kHz), meaning it can filter out 99.8% of noise at a frequency of 10 kHz.

Furthermore, by eliminating the capacitor, the size has been reduced compared to existing hybrid structures. When fabricated using a 28 nm CMOS process, its size is only 0.032 mm². Reducing the size allows more LDOs to be integrated into a chip, making it more suitable for high-performance chips like system-on-chip (SoC) devices that integrate multiple functional blocks.

Structure of the developed LDO circuit (above) and a photo of the actual LDO packaged in chip form (below).

Changmin Ahn, the first author of the study, explained, "In typical hybrid structures, the transition from digital to analog is not smooth, so a capacitor is included in the circuit as a buffer. We addressed this issue with new circuit design methods called seamless digital-to-analog transition (D2A-TF) and LGG (Local Ground Generator)."

This LDO is designed so that the digital circuit only activates during events where the current changes rapidly, minimizing standby power consumption. It recorded a world-leading performance figure of merit (FoM) of 0.029 ps, which comprehensively evaluates standby current, voltage stabilization speed, and noise suppression capability.

Professor Heein Yoon stated, "As an ultra-compact, low-power circuit with outstanding voltage stabilization and noise suppression, it can be widely used in the development of system-on-chip solutions for AI semiconductors, 6G communication chips, and more."

This research was published on September 3 in the Journal of Solid-State Circuits, a prestigious journal in the field of circuit design issued by the IEEE Solid-State Circuits Society.

The research was supported by the Ministry of Science and ICT, the Semiconductor Design Education Center, and the Regional Intelligence Innovation Talent Development Project of the Institute for Information and Communications Technology Planning and Evaluation (IITP) under the Ministry of Science and ICT.

This content was produced with the assistance of AI translation services.