Successful Localization of Copper Plating Solution for Semiconductors... "Aiming for Exports to Japan"

Dr. Minhyung Lee (left) and a researcher at Saenggiwon testing semiconductor copper plating solution

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[Asia Economy Reporter Kim Bong-su] The Korea Institute of Industrial Technology announced on the 31st that it has independently developed a world-class high-performance copper plating solution technology for semiconductors, achieving the highest level of plating film flatness, and has launched a product in collaboration with a technology transfer company, marking the first domestic production.

The "copper plating solution," essential for semiconductor packaging, is currently entirely imported from Japan and the United States, making it the only material in the entire semiconductor process with a "domestication rate of zero (0%)." This material is mainly used in the "bumping" process, which plates copper onto circuit patterns engraved on wafers to give those parts electrical properties.

As semiconductor circuit patterns have recently miniaturized to the scale of several nanometers (nm), it has become urgent to develop high-flatness copper plating solutions and achieve material independence at a corresponding level to continuously maintain the competitiveness of the world's number one semiconductor industry.

Dr. Min-Hyung Lee's research team at the Eco-friendly Thermal Surface Treatment Division of the Korea Institute of Industrial Technology conducted about 15,000 experiments over three years and identified the optimal organic additives and their mixing ratios among various additives that control the plating film surface flatness. They achieved a world-class high flatness with plating thickness variation within "2%." Typically, after plating, the surface becomes convex like water droplets, but the flatter the surface, the more evenly the current is delivered, improving production yield and final product performance. The secret to the developed plating solution's high flatness lies in the golden mixing ratio of two additives, the "convex shape inducer" and the "concave shape inducer," discovered based on the principle of thesis-antithesis-synthesis, where combining convex and concave shapes results in a flat surface.

According to process tests conducted by actual demand companies, it was possible to secure high flatness with plating thickness variation within "2%" at a high-speed plating rate of up to 3 micrometers (μm) per minute, showing about a 150% improvement in productivity compared to existing foreign materials. Another advantage is that the numerous additive mixing experiment results accumulated so far have been databased, enabling the production of customized plating solutions with convex or concave characteristics as desired by demand companies.

The research team transferred the technology to a domestic electronic materials specialized company in December 2020 and launched the product. Over the past six months, it has been undergoing test evaluations in semiconductor manufacturing processes of major companies. Since the transferred technology was developed from the start of R&D with mass production in mind rather than just laboratory level, considering all plating conditions and variables, the process from technology transfer to product launch and major company test evaluation was completed swiftly within eight months. Currently, positive feedback is being received from the major company, confirming that the plating characteristics required for manufacturing 12-inch large wafers and next-generation semiconductor products are fully satisfied. If the evaluation is successfully completed within the next few months, the first domestication of plating materials and equipment, which account for about 80% of domestically produced semiconductor products, will be achieved, and it is expected that reverse exports to material powerhouses such as Japan will also be possible.

Dr. Lee said, "The semiconductor plating solution market, worth about 200 billion KRW, is a small field for large companies to enter but requires high-level technology for small and medium enterprises, so domestication had been slow. This is the result of a public research institute fulfilling its role." He added, "Following the development of products for silicon through-via (TSV) for three-dimensional integrated circuits, we plan to expand research areas to high-performance tin-silver and indium plating solutions that can be used in various industries in the future."

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